Back ListLm3s101 microcontroller

summary



Ti stellaristm series microcontroller is the first one based on arm ® cortex tm-m3, which introduces high-performance 32-bit computing into price sensitive embedded microcontroller applications. These pioneering devices have the same price as 8-bit and 16 bit devices, but they can provide users with 32-bit device performance, and all devices are provided in small package form.



The lm3s101 microcontroller of stellaris series has many advantages of ARM microcontroller, such as the widely used development tools, the application of the underlying structure IP of SOC, and a large number of user groups. In addition, the controller uses the thumb-2 instruction set of arm compatible thumb ® to reduce the memory demand and cost.



Texas Instruments (TI) offers a complete set of solutions for fast market access, including user development boards, white papers and application manuals, as well as a strong network of support, sales and distributors.


characteristic

Lm3s101 microcontroller includes the following product features:

32-bit RISC performance

- 32-bit arm ® cortex tm-m3 v7m architecture optimized for small embedded applications

- thumb-2 specific instruction set processor core compatible with thumb ® for increased code density

- 20 MHz operation

- hardware division and single period multiplication

- Integrated nested vector interrupt controller to provide explicit interrupt handling

- 14 interrupts with 8 priorities

- non aligned data access enables data to be effectively compressed into memory

- bit banding maximizes memory usage and provides innovative peripheral control

Internal memory

- 8KB single cycle flash

User managed flash block protection based on 2KB block size

Flash data programming for user management

User defined and managed flash protection block

- 2KB single cycle SRAM

Universal timer

- 2 timers, each configurable as a 32-bit timer or two 16 bit timers

- 32 bit timer mode:

Programmable one shot timer

Programmable cycle timer

Real time clock with external 32.768-KHz clock as input

During debugging in cycle and single trigger mode, when the controller makes the halt flag of CPU effective, the stall operation can be controlled by the user

- 16 bit timer mode

General timer function with 8-bit Prescaler

Programmable single trigger timer

Programmable cycle timer

During debugging, when the controller makes the halt flag of CPU valid, the stall operation can be controlled by the user

- 16 bit input capture mode

Input edge count capture

Input edge time capture

- 16 bit PWM mode

Simple PWM mode, the output phase reversal of PWM signal can be programmed by software

Watchdog timer that can follow arm firmspecification

- 32-bit down counter with programmable load register

- independent watchdog clock with Enable

- programmable interrupt generation logic with interrupt mask

- provide lock register protection to prevent software runaway

- reset generation logic with enable / disable

- during debugging, when the controller makes the halt flag of CPU valid, the stall operation can be controlled by the user

Synchronous serial interface (SSI)

- Master or slave operation

- programmable clock bit rate and Prescaler

- independent transmit and receive FIFO, 16 bit wide, 8 unit deep

- programmable interface operation of Freescale SPI, microwire or Texas tool synchronous serial interface

- programmable data frame size from 4 to 16 bits

- internal loopback test mode for diagnostic / commissioning tests

UART

- fully programmable 16C550 type UART

- independent 16 × 8 transmit (TX) and 16 × 12 receive (Rx) FIFO to reduce CPU interrupt service load

- programmable baud rate generator with fractional frequency divider

- programmable FIFO length, including 1-byte operation to provide common double buffer interface

- FIFO trigger points are 1 / 8, 1 / 4, 1 / 2, 3 / 4 and 7 / 8

- standard asynchronous communication bits for start, stop and parity

- error start bit detection

- line break generation and detection

Analog comparator

- two independent integrated analog comparators



- configurable output to drive output pin or generate interrupt



- compare external pin input to external pin input or to internal programmable voltage reference



GPIO



- 2 to 18 gpios, depending on configuration



- interrupt generation programmable as edge trigger or level detection



- bit masking through address lines in read and write operations



- programmable control of GPIO port configuration



Weak pull-up or pull-down resistance



2-ma, 4-ma, and 8-ma port drives



Slope control of 8-ma drive



Open drain enable



Digital input enable



Power Supply



- on chip linear voltage regulator (LDO), with user adjustable 2.25V ~ 2.75V programmable output



- on the controller